1. Field of the Invention
The present invention relates to an SRAM (static random access memory), especially to a multi-port SRAM module.
2. Description of Related Art
FIG. 1 illustrates a circuit of a conventional dual port SRAM module. This figure shows a plurality of dual port memory cells 110 situated at the same row of a memory cell array in the dual port SRAM module. The dual port memory cells 110 are all connected to the same group of word lines WLA and WLB but each is connected to different bit line pairs PBLA and PBLB, each of which includes 2 bit lines. FIG. 2 illustrates a circuit of the dual port memory cell 110, which is typically made of 8 transistors. 4 of the 8 transistors form a latch 112, 2 transistors 113 and 114 form one port of the dual port memory cell 110, which is connected to the word line WLA, and the other 2 transistors 115 and 116 form the other port of the dual port memory cell 110, which is connected to the word line WLB. The word line WLA controls whether one port is open or close, namely, whether or not the latch 112 is connected to the bit line pair PBLA (including a bit line BLA and a bit line/BLA); the word line WLB controls whether the other port is open or close, namely, whether or not the latch 112 is connected to the bit line pair PBLB (including bit line BLB and bit line/BLB). Referring back to FIG. 1, the word line WLA and the word line WLB are respectively driven by an inverter 120 and an inverter 130. The output of the inverter 120 is coupled to one port of the dual port memory cell 110 and the output of the inverter 130 is coupled to the other port of the dual port memory cell 110. A dual port SRAM has advantages of enhanced access speed but also has some disadvantages, such as (a) the latch 112 suffering double read disturb as the dual port memory cell 110 being read through both bit lines pairs PBLA and PBLB at the same time, which degrades read static noise margin (RSNM); (b) as a read operation and a write operation being performed on a dual port memory cell 110 at the same time, the write margin is degraded because a write current competes with a read current; and (c) when two word lines WLA and WLB of the same row are asserted at the same time, a dual port memory cell 110 in a data-retaining state suffering from a high possibility of data loss of the latch due to increased leakage current.